1. Field of the Invention
The present invention relates to a semiconductor device in which a transistor different in operating voltage from one another and a resistor are embedded on the same semiconductor substrate, and a method of manufacturing the same.
2. Description of the Related Art
An increase in gate leakage current in silicon oxide system gate insulating film, and deplation in a polysilicon based gate electrode have become problems with promotion of high integration of MISFETs. As measures taken to cope with such problems, adoption of a gate stack structure having a gate insulating film having a higher permittivity larger than that of a silicon oxide, and a metallic gate (hereinafter referred to as “a high permittivity film/metallic gate”) is discussed for high-speed operation and low-power consumption MIS type transistors. However, utilizing a normal manufacturing method results in that a heat history after the high permittivity film/metallic gate is formed is high. As a result, there is encountered such a problem that the characteristics and reliability of the high-permittivity insulating film are deteriorated, and a value of a work function of the metallic gate shifts from a design value.
In order to solve this problem, a buried gate (for example, a damascene gate) structure is proposed. This buried gate structure is obtained by completing a prime heat treatment process necessary for transistor formation before the high permittivity film/metallic gate is formed. The technique relating to this buried gate structure, for example, is described in Japanese Patent Laid-Open No. 2001-102443. A method of forming this buried gate structure when a metallic electrode, for example, is used is described as follows. That is to say, a gate insulating film and a gate electrode portion are removed once after a transistor structure having a silicon oxide system gate insulating film and a polysilicon based gate electrode is formed, and a metal system oxide film and a metallic electrode are newly buried therein. According to this method, the metallic electrode is prevented from being deteriorated because the heat treatment necessary for the transistor formation is completed before completion of the formation of the metallic electrodes.
However, the high-speed operation and the low-power consumption are required for the actual semiconductor devices. For this reason, in order to meet these requirements, a transistor adopting the metal system oxide film and the metallic electrode, and a transistor adopting a conventional silicon oxide system gate insulating film and the polysilicon based gate electrode of the related art for the high voltage operation are mixedly formed in the actual semiconductor device. Therefore, the damascene gate structure having the high permittivity film/metallic gate for the high-speed operation and low-voltage operation, and a gate structure having a thicker gate insulating film showing a high withstand voltage must be formed on the same semiconductor substrate of the same chip in the embedded manner.
Moreover, in addition to the transistor adopting the metal system oxide film and the metallic electrode, and the transistor adopting the silicon oxide system gate insulating film and the polysilicon based gate electrode of the related art for the high-voltage operation, a polysilicon resistor needs to be embedded on the semiconductor substrate. An example of a method of manufacturing the semiconductor device in the related art will now be described with reference to cross sectional views, showing manufacturing process, of FIGS. 9A to 9I.
As shown in FIG. 9A, device isolation regions 12 are formed in a semiconductor substrate 11 by carrying out a device isolation process. In this case, for example, a region LVN and a region LVP in which low-voltage transistors (such as MISFETs) are intended to be formed, respectively, a region MV/HV in which a middle-voltage transistor and a high-voltage transistor (such as MISFETs) are intended to be formed, and a region MR in which a resistor is intended to be formed are isolated from one another by these device isolation regions 12. Also, both the region MV/HV and the region MR are given as a generic name of a first region 11A, and both the region LVN and the region LVP are given as a generic name of a second region 11B. Regions on the semiconductor substrate 11 which are isolated from one another by these device isolation regions 12 become active regions, respectively.
Next, an ion implantation for forming a P-type well region (not shown), an ion implantation for forming a buried layer (not shown) for blocking punch-through of a MISFET, and an ion implantation for adjusting a threshold voltage (Vth) are suitably performed for a region in which an N-channel MISFET is intended to be formed, thereby an NMOS channel is formed. In addition, an ion implantation for forming an N-type well region, an ion implantation for forming a buried layer (not shown) for blocking punch-through of a MISFET, and an ion implantation for adjusting a threshold voltage (Vth) are suitably performed for a region in which a P-channel MISFET is intended to be formed, thereby a PMOS channel region is formed. At this time, the ion implantation may be performed for the region MV/HV in which the middle-voltage transistor and the high-voltage transistor are intended to be formed, and the regions LVN and LVP in which the low-voltage transistors are intended to be formed under the respective ion implantation conditions.
Next, a gate insulating film 13 is formed on the surface of the region MV/HV of the semiconductor substrate 11. The high-voltage transistor and the middle-voltage transistor tend to have thick gate insulating films, respectively, in many cases. Thus, the gate insulating film 13, for example, is formed from a silicon oxide film. The silicon oxide film is formed by, for example, performing the thermal oxidation at 750 to 900° C. to have a thickness of 2 to 4 nm. The gate insulating film 13 is formed on each of the active regions of the region MR of the first region 11A, and the second region 11B concurrently with the formation of that gate insulating film 13 on the surface of the region MV/HV. In this case, however, the gate insulating film 13 is used as an insulating film 61 in the region MR and is also used as a dummy gate insulating film 14 in the second region 11B.
Next, a silicon based material layer 71 from which a first gate electrode, a resistor main portion, and dummy gate electrodes are each intended to be formed is formed on the gate insulating film 13, the insulating film 61, and the dummy gate insulating films 14. The silicon based material layer 71 is formed over the entire surface by, for example, depositing a polysilicon, amorphous silicon or silicon germanium layer over the entire surface through the gate insulating film 13, the insulating film 61, and the dummy gate insulating films 14 on the semiconductor substrate 11. When the silicon based material layer 71, for example, is formed from the polysilicon layer, a low-pressure CVD (LP-CVD) method is utilized. In this case, monosilane (SiH4) is used as a raw material gas and a deposition temperature is set at 580 to 620° C. Under this condition, the polysilicon layer is deposited to have a thickness of 100 to 150 nm, for example, 150 nm.
Next, there is performed an ion implantation process for reducing a gate resistance. By utilizing a resist application technique and a lithography technique, a resist film (not shown) is formed on the silicon based material layer 71, and an opening portion is formed so as to expose the region MV/HV in the first region 11A. Subsequently, in order to reduce the gate resistance of the silicon based material layer 71 in the region MV/HV, an ion implantation is performed for the silicon based material layer 71 in the region MV/HV. As an example, in the case of the P-channel MISFET, boron (B) ions are implanted into the silicon based material layer 71 in the region MV/HV at an implantation energy of 5 keV with a dose of 8×1015/cm2. On the other hand, in the case of the N-channel MISFET, phosphorus (P) ions are implanted into the silicon based material layer 71 in the region MV/HV at an implantation energy of 10 keV with a dose of 8×1015/cm2. The ion implantation condition is merely an example, and thus the condition can be suitably selected. After that, the resist film described above is removed away by, for example, performing ashing and by using a mixed liquid of a sulfuric acid and a hydrogen peroxide.
Next, likewise, by utilizing the resist application technique and the lithography technique, a resist film (not shown) is formed on the silicon based material layer 71, and an opening portion is formed so as to expose the region MR in the first region 11A. Subsequently, in order to determine a resistance value of the silicon based material layer 71 in the region MR, an ion implantation is performed for the silicon based material layer 71 in the region MR. As an example, boron (B) ions are implanted into the silicon based material layer 71 in the region MR at an implantation energy of 15 keV with a dose of 3×1015/cm2. The ion implantation condition is merely an example, and thus the condition can be suitably selected. After that, the resist film described above is removed away by, for example, performing the ashing and by using the mixed liquid of a sulfuric acid and a hydrogen peroxide.
As shown in FIG. 9B, a hard mask layer 74 is formed on the silicon based material layer 71 (refer to FIG. 9A). A silicon nitride (SiN) layer is deposited to have a thickness of, for example, about 50 to about 100 nm by, for example, utilizing the LP-CVD method, thereby forming the hard mask layer 74. In this case, the silicon nitride layer is formed to have the thickness of 80 nm.
Next, by utilizing the resist application technique and the lithography technique, a resist pattern (not shown) for formation of the first gate electrode and the dummy gate electrodes is formed on the hard mask layer 74. After that, the hard mask layer 74 is processed with the resist pattern as an etching mask by, for example, utilizing an anisotropic etching method, thereby forming a hard mask 74A for formation of the first gate electrodes of the high-voltage transistor and the middle-voltage transistor, and hard masks 74B for formation of the dummy gate electrodes of the low-voltage transistors, and a hard mask 74C for formation of the resistor in the first region 11A, the second region 11B, and the first region 11A, respectively. In the anisotropic etching method, hydrogen bromide (HBr) chlorine (Cl) system gas, for example, is used as etching gas. Moreover, dummy gate electrodes 16, and a resistor main body 62 are formed in the second region 11B and in the first region 11A, respectively, at the same time that a first gate electrode 15 is formed in the first region 11A by using the hard masks 74A, 74B and 74C as an etching mask. At this time, the gate insulating film 13, the dummy gate insulating films 14, and the insulating film 61 are partially etched away.
In such a manner, a gate portion 17 is composed of the hard mask 74A, the first gate electrode 15, and the gate insulating film 13. Each of dummy gate portions 18 is composed of the hard mask 74B, the dummy gate electrode 16, and the dummy gate insulating film 14. Also, a resistor portion 64 is composed of the hard mask 74C, the resistor main body 62, and the insulating film 61.
Next, as shown in FIG. 9C, sidewall portions of the gate portion 17, the dummy gate portions 15 and the resistor portion 64 are oxidized. Moreover, offset spacers (not shown) are formed on the sidewall portions of the gate portion 17, the dummy gate portions 15 and the resistor portion 64, respectively. Next, extension regions 21 and 22 are formed on a surface side of the semiconductor substrate 11 and below both sides of each of the gate portion 17 and the resistor portion 64 in the first region 11A, respectively. Extension regions 23 and 24 of an N-channel MISFET are formed on the surface side of the semiconductor substrate 11 and below both sides of the dummy gate portion 18 of the region LVN in the second region 11B, respectively. Also, extension regions 25 and 26 of a P-channel MISFET are formed on the surface side of the semiconductor substrate 11 and below both sides of the dummy gate portion 18 of the region LVP in the second region 11B, respectively.
Next, sidewalls 20 are formed on side portions of the gate portion 17, the dummy gate portions 18, and the resistor portion 64 through the offset spacers (not shown), respectively.
Next, source/drain regions 27 and 28 are formed on the surface side of the semiconductor substrate 11 and below the both sides of each of the gate portion 17 and the resistor portion 64 in the first region 11A through the corresponding ones of the extension regions 21 and 22, respectively. In addition, source/drain regions 29 and 30 are formed on the surface side of the semiconductor substrate 11 and below the both sides of the dummy gate portion 18 of the region LVN in the second region 11B through the extension regions 23 and 24, respectively. Moreover, source/drain regions 31 and 32 are formed on the surface side of the semiconductor substrate 11 and below the both sides of the dummy gate portion 18 of the region LVP in the second region 11B through the extension regions 25 and 26, respectively.
Next, as shown in FIG. 9D, a silicide layer 33 is formed on each of the source/drain regions 27 to 32. After that, an interlayer insulating film is formed over the entire surface of the semiconductor substrate 11 so as to cover the gate portion 17, the dummy gate portions 18, the resistor portion 64, and the like. Before this process, firstly, a liner film 36 is formed over the entire surface of the semiconductor substrate 11, and a first interlayer insulating film 38 becoming that interlayer insulating film is formed on the liner film 36. Next, the first interlayer insulating film 38 and the liner film 36 which are formed so as to cover the gate portion 17, the dummy gate portions 18, the resistor portion 64 and the like are polished by utilizing a chemical mechanical polishing (CMP) method until the hard masks 74A, 74B and 74C are exposed. At this time, the hard masks 74A, 74B and 74C are left.
As shown in FIG. 9E, the hard mask 74A (refer to FIG. 9D) on the first gate electrode 15 in the first region 11A, the hard masks 74B (refer to FIG. 9D) on the dummy gate electrodes 16 in the second region 11B, and the hard mask 74C (refer to FIG. 9D) on the resistor main body 62 in the first region 11A are removed away by utilizing either a dry etching method or the CMP method. When the hard masks 74A, 74B and 74C are removed away by, for example, utilizing the CMP method, the surfaces of the first gate electrode 15, the dummy gate electrodes 16, the resistor main body 62, the first interlayer insulating film 38, the liner film 36, the sidewalls 20, and the like are planarized to have approximately the same flat surface-like shape.
As shown in FIG. 9F, an etching mask (not shown) is formed so as to cover the first region 11A by utilizing the resist application technique and the lithography technique. Also, the dummy gate electrodes 16 (refer to FIG. 9E) are removed away by, for example, utilizing a dry etching method, thereby forming trenches 42 for gate formation, respectively. After that, the etching mask is removed away. Moreover, the dummy gate insulating films 14 (refer to FIG. 9B) are removed away by utilizing a wet etching method using a dilute hydrofluoric acid, thereby completing the trenches 42 for gate formation, respectively. At this time, upper portion of the first interlayer insulating film 38 is also etched away.
As shown in FIG. 9G, a second gate insulating film 43 is formed on each of inner surfaces of the trenches 42 for gate formation. Next, a hafnium silicide (HfSix) layer is deposited in the region LVN through the second gate insulating film 43 so as to be formed on each of the inner surfaces of the trenches 42 for gate formation to have a thickness of, for example, about 10 to about 100 nm, thereby forming a work function controlling film 44 for determining a work function. In addition, a titanium nitride (TiN) layer is deposited in the region LVP to have a thickness of about 5 to about 50 nm, thereby forming a work function controlling film 45 for determining a work function.
Next, a conductive film 46 made of a conductive material is formed so as to be filled in each of the insides of the trenches 42 for gate formation. The conductive film 46, for example, is made of tungsten (W) as a metallic material having a lower electrical resistance value than that of each of the work function controlling films 44 and 45.
As shown in FIG. 9H, there is removed the extra conductive film 46 (refer to FIG. 9G) other than the conductive film 46 filled in each of the insides of the trenches 42 for gate formation. This removal process is carried out by, for example, utilizing the CMP method. In the phase of utilizing the CMP method, the liner film 36, the first interlayer insulating film 38, and the like serve as a polishing stopper. As a result, the second gate electrode 47 of the low-voltage transistor (N-channel MISFET) in the second region 11B is formed from the conductive film 46 and the work function controlling film 44 which are left in the corresponding one of the trenches 42 for gate formation. Also, the second gate electrode 48 of the low-voltage transistor (P-channel MISFET) in the second region 11B is formed from the conductive film 46 and the work function controlling film 45 which are left in the corresponding one of the trenches 42 for gate formation.
Although the second gate electrode 48 is formed in the second region 11B by utilizing the CMP method, at this time, trimmed portions are generated in the silicon based materials of which the resistor main body 62 in the region MR, and the first gate electrode 15 in the region MV/HV are made, respectively. Since an amount of trimming, for example, is not constant within the surface of the semiconductor substrate 11, there are caused a problem that the resistance value of the first gate electrode 15 increases, and a problem that the resistance values of the first gate electrode 15 and the resistor main body 62 disperse.
In addition, as shown in FIG. 9I, a protective film 41 is formed over all the surfaces of the first interlayer insulating film 38, the liner film 36, and the like. Also, an opening portion 50 is formed in a portion of the protective film 41 corresponding to the region MV/HV. Next, a nickel layer, for example, is formed as a metallic layer for formation of a silicide layer over the entire surface. Also, an rapid thermal anneal (RTA), for example, is performed at 350° C. for 30 seconds, so that the nickel layer is reacted with only silicon (Si) of the first gate electrode 15, thereby forming a silicide layer 40. After that, unreacted nickel is removed away by utilizing a wet etching method. Subsequently, a heat treatment is performed, thereby forming a nickel silicide (NiSi2) layer having a low resistance value. This heat treatment, for example, is performed as the RTA at a temperature of 450° C. or less allowing reduction in resistance value for 30 seconds.
As has been described above, the formation of the silicide layer 40 on the first gate electrode 15 results in that the reduction in resistance value due to the formation of the silicide layer 40 compensates for the increase in resistance value due to the trimming of the upper portion of the first gate electrode 15. However, there still remains the problem that the resistance value of the resistor main body 62 having the trimmed upper portion disperses.
In addition, as shown in FIG. 10, the second gate electrodes 47 and 48 of the second region 11B are formed after the protective film 41 is formed in the first region 11A, thereby making it possible to solve the problem that the upper portions of the first gate electrode 15 and the resistor main body 62 are trimmed. Moreover, there is caused a problem that the conductive film 46 used to form the second gate electrodes 47 and 48 partially remains in an end portion of the protective film 41. As has been described above, the formation of the protective film 41 causes another problem that the conductive film 46 partially remains in the end portion of the protective film 41, and thus does not basically solve the problem that the upper portion of the resistor main body 62 is trimmed.
The technique described above, for example, is also described in Japanese Patent Laid-Open No. 2004-6475.